Master Thesis - Design of a 5.2 GHz DRO/PLL

The master thesis equals 30p in the MScEE program.

A DRO, or Dielectric Resonator Oscillator, is an oscillator topology that is used for fixed frequency sources. The dielectric material of the resonator has very high Q which reduces the usable bandwidth to no more than a few MHz, which for a fixed frequency source is good, and when used together with a active device, transistor, it can be used as the resonator of a voltage controlled oscillator. However, it is mandatory that such a oscillator is used in a Phase Locked Loop (PLL) in order to keep it oscillating at its wanted frequency. The task involves selection of the active device (i.e. the transistor) of the oscillator, and the appropriate dielectric material for the resonator. Selection of the oscillator topology (i.e. Colpitt, Hartley, etc.) shall also be made for this work. The work also involves the design, manufacturing and test of the complete oscillator: transistor matching, resonator design, as well as PLL.

For more information about the master thesis, please contact:

Robert Petersson, telephone +46 31 735 40 05, 

J├Ârgen Nilsson, telephone +46 31 735 44 17,

Apply here